The present invention relates to a semiconductor device and a method for fabricating the same, and in particular to a structure of a MOS transistor and a method for fabricating the same for constituting an input/output buffer circuit having a CMOS structure.
FIG. 11 shows a sectional view of a conventional NMOS transistor. As shown in FIG. 11, the transistor comprises a semiconductor substrate 101, and element isolation regions 102 formed on the surface of an inactive region of the semiconductor substrate 101. A P-well 103 is formed up to a predetermined depth from the surface of the semiconductor substrate 101, and source/drain regions 104 containing N-type impurities are formed on the surface of the semiconductor substrate 101. A channel region 105 is formed between two source/drain regions 104. A gate oxide film 106 is formed on the channel region 105, and a gate electrode 107 is formed on the gate oxide film 106. Further, a side wall 108 is formed on the lateral section of the gate electrode 107.
Further, though not illustrated in the sectional view of FIG. 11, a contact is formed respectively on the surface of the source/drain regions 104 which appears in cross section in the gate length direction.
Furthermore, in the case of a device in which the NMOS transistor in FIG. 11 follows a design rule of 0.6 xcexcm or less, the P-well 103 has at most an impurity concentration of approximately. 3.0 E17/cm3.
When the maximum impurity concentration of the P-well 103 is more than 3.0 E17/cm3, junction capacitance of an N-type high impurity concentration region of the source/drain regions 104 increases, and as a result, electrical characteristics of the NMOS transistor deteriorate.
Moreover, as the semiconductor device is reduced in size, the impurity concentration in the well tends to be increased. Then, the capacitance of the PN junction between the P-well 103 and the source/drain regions 104 increases. As a result, in the product specification, the criterion of 10 pF or less of input/output capacitance in an input/output buffer portion can be hardly met.
In the following, a method for fabricating a semiconductor device having a CMOS structure including the NMOS transistor in FIG. 11 is described with reference to FIGS. 12(a) to 12(d).
FIG. 12(a) shows a sectional structure of a transistor to be finally obtained, in which a PMOS transistor forming portion is shown at the left, an NMOS transistor forming portion is shown at the center, and a memory cell forming portion is shown at the right.
First, as shown in FIG. 12(b), a mask 109 is formed on an NMOS transistor forming region and a memory-cell forming region on the semiconductor substrate 101 having the element isolation region 102 serving as an inactive region, and N-type impurities are implanted into a PMOS transistor forming region to form an N-well 110 using the mask 109 as an ion implantation mask. Thereafter, the mask 109 is removed.
Then, as shown in FIG. 12(c), a mask 111 is formed on a PMOS transistor forming region, and P-type impurity ions are implanted into an NMOS transistor forming region and a memory cell forming region to form a P-well 103 by using the mask 111 as an ion implantation mask. Therefore, the mask 111 is removed.
Thereafter, as shown in FIG. 12(d), a mask 112 is formed on PMOS and NMOS transistor forming regions, and impurities are implanted to form a threshold adjustment layer 113 on the surface of an active region of the memory cell forming region. Therefore, the mask 112 is removed.
Further, as shown in FIG. 12(a), gate oxide films 106 and 115 and gate electrodes 107 and 116 are formed in order. The source/drain regions 104 and 114 are formed by implanting N- or P-type impurities into the regions respectively. Then, side walls 108 and 117 are formed on the lateral sections of the gate electrodes 107 and 116. Thus, the transistor shown in FIG. 12(a) is formed. The threshold adjustment layer 113 is not illustrated in FIG. 12(a) for simplicity.
A semiconductor device comprising transistors of a ICMOS structure may be obtained by following the above fabrication steps. However, as already described, the transistor having the structure shown in FIG. 12(a) has a problem in that capacitance increases in the PN junction formed with a well and a source/drain region.
FIG. 13 shows the structure of a NMOS transistor which has a reduced junction capacitance. The structure of the NMOS transistor shown in FIG. 13 is different from that of the NMOS transistor shown in FIG. 11 in that a threshold adjustment layer 105a is formed in a region serving as a channel including ends of the two adjacent source/drain regions 104, and the impurity concentration of the P-well 103 is lower than that of the P-well 103 of the transistor shown in FIG. 11.
Generally, the threshold adjustment layer 105a is formed on the entire surface layer of an active region. However, in this case, the layer 105a is formed only on a channel region. Therefore, the impurity concentration of the P-well 103 which is located just under the source/drain region 104 with high concentration N type impurity may be made lower than that of the threshold adjustment layer 105a. Thus, the junction capacitance of the source-drain region 104 with the underling P-well 103 is decreased to a certain extent.
A method for fabricating a semiconductor device having a CMOS structure including the transistor shown in FIG. 13 is shown in FIG. 14(a) to FIG. 14(c).
First, similar steps as shown in FIGS. 12(b) and 12(c) are performed. Then, as shown in FIG. 14(a), a mask 118 is formed on the PMOS transistor forming region and on the NMOS transistor forming region except the channel region thereof. Then, P-type impurity ions are implanted with the mask 118 as an ion implantation mask to form the threshold adjustment layer 105a on the channel portion of the NMOS transistor forming region, and also to form the threshold adjustment layer 105a with the same concentration on the entire surface of the active region of a memory cell forming region. Thereafter, the mask 118 is removed.
Then, similarly as shown in FIG. 12(d), the mask 112 is formed on the PMOS and NMOS transistor forming regions. Then, ions are additionally implanted into the memory cell region to form the threshold adjustment layer 113 as shown in FIG. 14(b). Thereafter, the mask 112 is removed.
Thereafter, the similar steps as explained with reference to FIG. 12(a) are performed, and thus the semiconductor device having a CMOS structure shown in FIG. 14(c) is obtained. As described above, this structure is different from that of the MOS transistor shown in FIG. 12(a) particularly in that the threshold adjustment layer 105a is formed in a region serving as the channel region of an NMOS transistor. Since the threshold adjustment layer 105a is formed, the impurity concentration of the P-well 103 underlying the source/drain region may be reduced 104. Therefore, the junction capacitance between the source/drain region 104 and the P-well 103 may be reduced to a certain extent.
However, in the fabrication method as shown in FIG. 14(a) to FIG. 14 (c), the number of steps is increased compared to the fabrication method of the normal semiconductor device having a CMOS structure such as an SRAM as shown in FIG. 12. An additional mask (reticle), which is not necessary for normal SRAM fabrication, is required to form the mask 118 and to perform ion implantation. Therefore, fabrication cost is increased as the number of steps is increased.
With regard to the semiconductor substrate 101 as shown in FIG. 11 to FIG. 14(d), an N-type substrate is used for a CMOSSRAM, and a P-type substrate is used for a Bi-CMOSSRAM which includes bipolar transistors.
Another method for reducing the junction capacitance of a MOS transistor is disclosed in Japanese Patent Application Laid-Open No. 7-193134. In the method, a MOS transistor comprised in a logic circuit portion is fabricated so as to have a structure almost the same as that shown in FIG. 13. In the case of this structure, the channel ion implantation region 105a (i.e. a threshold adjustment layer 105a in FIG. 13) is formed only nearby the gate electrode 107, and thereby the junction capacitance between the source/drain region 104 and the channel ion implantation region 105a is reduced. Moreover, in MOS transistors for forming memory cells, channel ions are implanted to the whole active region and to element isolation regions 102 passing through a field oxide film. Ions are increased in the field separation regions underneath the element isolation regions 102, and thereby field separation width may be reduced. Thus, integration density is improved.
However, in the case of the MOS transistor disclosed in Japanese Patent Application Laid-Open No. 7-193134, the channel ion implantation regions of the logic circuit portion and of the memory cell region are simultaneously formed, and therefore slight adjustment of a threshold value is difficult. Moreover, similarly to the case shown in FIG. 14, in order to implant ions for threshold adjustment into the channel region of the MOS transistors for memory cells, an additional mask is needed than the case of fabricating a conventional CMOSSRAM. Therefore, the fabrication process is complicated and fabrication cost is increased.
Moreover, the MOS transistor disclosed in Japanese Patent Application Laid-Open No. 7-193134 has a normal well structure, in which the whole transistor is formed on a P-well similarly to the case of the MOS transistor shown in FIG. 13. Therefore, it is possible to reduce junction capacitance at the boundary between the source/drain region and the P-well region to a certain extent, but it is difficult to greatly reduce the junction capacitance.
It is already described that the input/output capacitance of an input/output buffer portion increases as the junction capacitance between the source/drain region 104 and the P-well 103 increases. An input/output circuit is shown in FIG. 15 in conjunction with this problem.
As shown in FIG. 15, the output side and the input side of the input/output circuit respectively comprises an NMOS transistor and a PMOS transistor. Two transistors are connected each other at the output side, and the potential at a node between the two transistors is output and supplied to the gate electrodes of the two transistors at the input side. Moreover, the potential of the pad is equal to the output potential of the output side and the input potential of the input side.
The input/output capacitance of the input/output circuit is almost equal to the sum of the input-side gate capacitance and the output-side source/drain capacitance. The input-side gate capacitance depends on the thickness of the gate oxide film of the MOS transistor and increases as the thickness of the oxide film decreases. The output-side source/drain capacitance is determined in accordance with the well and source/drain concentration of the MOS transistor. Because a heavy current flows through the output-side transistor, the transistor has a large size, such as a gate width W of approximately several hundreds of microns, and thereby the junction capacitance of this portion is larger than of other portions.
In the conventional semiconductor device as described above, reduction of input/output capacitance to meet a product specification has become difficult. In the method to form a threshold adjustment layer 105a as shown in FIG. 13, reduction of input/output capacitance is achieved to a certain extent, however, the number of fabrication steps is increased.
Therefore, the purpose of the present invention is to provide a semiconductor device and a method of fabrication thereof which shows a reduced input/output capacitance without increasing number of fabrication steps.
According to one aspect of the present invention, a semiconductor device comprises at least a first and a second MOS transistor of the same conduction type formed on a semiconductor substrate. The first MOS transistor is formed in a well with a first impurity concentration. The second MOS transistor includes a channel region, a source region and a drain region. The channel region of the second MOS transistor, a region under the channel region and a region under an element isolation region located around the second MOS transistor are formed in each region of a first impurity concentration. The source region and drain region of the second MOS transistor are formed in contact with a region of a second impurity concentration, and the first impurity concentration is larger than the second impurity concentration.
In another aspect of the present invention, in the semiconductor device, the region of a first impurity concentration is formed by wells, and the region of a second impurity concentration is formed by the semiconductor substrate.
In another aspect of the present invention, in the semiconductor device, the region of a first impurity concentration is formed by wells and the region of a second impurity concentration is formed by another well.
According to another aspect of the present invention, a semiconductor device comprises at least a first and a second MOS transistor of the same conduction type formed on a semiconductor substrate. The first MOS transistor is formed in a well with a first impurity concentration. The second MOS transistor includes a channel region, a source region and a drain region. One of the channel region plus a region under the channel region of the second MOS transistor or a region under an element isolation region located around the second MOS transistor is formed by a region of a first impurity concentration. The source and drain regions of the second MOS transistor and the other one of the channel region plus the region under the channel region of the second MOS transistor or the region under an element isolation region are formed in contact with a region of a second impurity concentration, and the first impurity concentration is larger than the second impurity concentration.
In another aspect of the present invention, in the semiconductor device, the region of a first impurity concentration is formed by a well, and the region of a second impurity concentration is formed by the semiconductor substrate.
In another aspect of the present invention, in the semiconductor device, the channel region plus a region under the channel region of the second MOS transistor is formed by a region of a first impurity concentration. The source and drain regions of the second MOS transistor and the region under the element isolation region are formed in contact with a region of a second impurity concentration.
In another aspect of the present invention, in the semiconductor device, the width of the element isolation region is set not less than 5.0 xcexcm.
In another aspect of the present invention, in the semiconductor device, the region under an element isolation region located around the second MOS transistor is formed by a region of a first impurity concentration. The source and drain regions of the second MOS transistor and the channel region plus the region under the channel region of the second MOS transistor are formed in contact with a region of a second impurity concentration.
In another aspect of the present invention, in the semiconductor device, the distance between a gate electrode of the second MOS transistor and a contact to a source region or a drain region is 0.5 to 3.0 xcexcm.
In another aspect of the present invention, in the semiconductor device, the second MOS transistor is applied for an output portion of an input/output buffer of the semiconductor device.
According to another aspect of the present invention, in a method for fabricating a semiconductor device including at least a first and a second MOS transistors, a well of a first impurity concentration are formed in a region for the first MOS transistor. Simultaneously, other wells of the first impurity concentration is formed under a channel region of the second MOS transistor and under an element isolation region surrounding the second MOS transistor. Regions of a second impurity concentration are formed for source and drain regions, and the second impurity concentration is lower than the first impurity concentration.